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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CNTEL0ACR, Counter-timer EL0 Access Control Register</h1><p>The CNTEL0ACR characteristics are:</p><h2>Purpose</h2>
        <p>An implementation of CNTEL0ACR in the frame at CNTBaseN controls whether the <a href="ext-cntpct.html">CNTPCT</a>, <a href="ext-cntvct.html">CNTVCT</a>, <a href="ext-cntfrq.html">CNTFRQ</a>, EL1 Physical Timer, and Virtual Timer registers are visible in the frame at CNTEL0BaseN.</p>
      <h2>Configuration</h2><p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether CNTEL0ACR is implemented in the Core power domain or in the Debug power domain.
    </p><p>Implementation of this register is <span class="arm-defined-word">OPTIONAL</span>.</p>
        <p>For more information, see <span class="xref">'Power and reset domains for the system level implementation of the Generic Timer'</span>.</p>
      <h2>Attributes</h2>
        <p>CNTEL0ACR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="22"><a href="#fieldset_0-31_10">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">EL0PTEN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8">EL0VTEN</a></td><td class="lr" colspan="6"><a href="#fieldset_0-7_2">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">EL0VCTEN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">EL0PCTEN</a></td></tr></tbody></table><h4 id="fieldset_0-31_10">Bits [31:10]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-9_9">EL0PTEN, bit [9]</h4><div class="field">
      <p>Second view read/write access control for the EL1 Physical Timer registers. This bit controls whether the <a href="ext-cntp_cval.html">CNTP_CVAL</a>, <a href="ext-cntp_tval.html">CNTP_TVAL</a>, and <a href="ext-cntp_ctl.html">CNTP_CTL</a> registers in the current CNTBaseN frame are also accessible in the corresponding CNTEL0BaseN frame.</p>
    <table class="valuetable"><tr><th>EL0PTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No access. Registers are <span class="arm-defined-word">RES0</span> in the second view.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Access permitted. If the registers are accessible in the current frame then they are accessible in the second view.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Timer reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-8_8">EL0VTEN, bit [8]</h4><div class="field">
      <p>Second view read/write access control for the Virtual Timer registers. This bit controls whether the <a href="ext-cntv_cval.html">CNTV_CVAL</a>, <a href="ext-cntv_tval.html">CNTV_TVAL</a>, and <a href="ext-cntv_ctl.html">CNTV_CTL</a> registers in the current CNTBaseN frame are also accessible in the corresponding CNTEL0BaseN frame.</p>
    <table class="valuetable"><tr><th>EL0VTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No access. Registers are <span class="arm-defined-word">RES0</span> in the second view.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Access permitted. If the registers are accessible in the current frame then they are accessible in the second view.</p>
        </td></tr></table>
      <p>The definition of this bit means that, if the Virtual Timer registers are not implemented in the current CNTBaseN frame, then the Virtual Timer register addresses are <span class="arm-defined-word">RES0</span> in the corresponding CNTEL0BaseN frame, regardless of the value of this bit.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Timer reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-7_2">Bits [7:2]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-1_1">EL0VCTEN, bit [1]</h4><div class="field">
      <p>Second view read access control for <a href="ext-cntvct.html">CNTVCT</a> and <a href="ext-cntfrq.html">CNTFRQ</a>.</p>
    <table class="valuetable"><tr><th>EL0VCTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p><a href="ext-cntvct.html">CNTVCT</a> is not visible in the second view.</p>
<p>If EL0PCTEN is set to 0, <a href="ext-cntfrq.html">CNTFRQ</a> is not visible in the second view.</p></td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Access permitted. If <a href="ext-cntvct.html">CNTVCT</a> and <a href="ext-cntfrq.html">CNTFRQ</a> are visible in the current frame then they are visible in the second view.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Timer reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-0_0">EL0PCTEN, bit [0]</h4><div class="field">
      <p>Second view read access control for <a href="ext-cntpct.html">CNTPCT</a> and <a href="ext-cntfrq.html">CNTFRQ</a>.</p>
    <table class="valuetable"><tr><th>EL0PCTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p><a href="ext-cntpct.html">CNTPCT</a> is not visible in the second view.</p>
<p>If EL0VCTEN is set to 0, <a href="ext-cntfrq.html">CNTFRQ</a> is not visible in the second view.</p></td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Access permitted. If <a href="ext-cntpct.html">CNTPCT</a> and <a href="ext-cntfrq.html">CNTFRQ</a> are visible in the current frame then they are visible in the second view.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Timer reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing CNTEL0ACR</h2>
        <p>CNTEL0ACR can be implemented in any implemented CNTBaseN frame.</p>

      
        <p><span class="xref">'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames'</span> describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:</p>

      
        <ul>
<li>Whether the CNTBaseN frame has virtual timer capability.
</li><li>Whether the corresponding CNTEL0BaseN frame is implemented.
</li><li>For an implementation that recognizes two Security states, whether the CNTBaseN frame, and any corresponding CNTEL0BaseN frame, is accessible by Non-secure accesses.
</li></ul>

      
        <p>If CNTEL0ACR is not implemented in an implemented CNTBaseN frame:</p>

      
        <ul>
<li>The register location in that frame is RAZ/WI.
</li><li>If the corresponding CNTEL0BaseN frame is implemented, the registers <a href="ext-cntfrq.html">CNTFRQ</a>, <a href="ext-cntp_ctl.html">CNTP_CTL</a>, <a href="ext-cntp_cval.html">CNTP_CVAL</a>, <a href="ext-cntp_tval.html">CNTP_TVAL</a>, <a href="ext-cntpct.html">CNTPCT</a>, <a href="ext-cntv_ctl.html">CNTV_CTL</a>, <a href="ext-cntv_cval.html">CNTV_CVAL</a>, <a href="ext-cntv_tval.html">CNTV_TVAL</a>, and <a href="ext-cntvct.html">CNTVCT</a> are not visible in that frame.
</li></ul>
      <h4>CNTEL0ACR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>Timer</td><td>CNTBaseN</td><td><span class="hexnumber">0x014</span></td><td>CNTEL0ACR</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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